1. Field of the Invention
This invention relates generally to interconnection of multiple electrical devices, and more particularly to interconnection of multiple ASIC devices, for example, multiple Field Programmable Gate Array (FPGA) devices.
2. Description of the Related Art
In the past, multiple FPGA devices have been interconnected as an array on a single circuit card using point-to-point or bussed parallel wiring configurations. Such configurations use many wires (along with associated I/O counts and termination components) to achieve required data transfer bandwidths, thus requiring the creation of many connection layers on a circuit card leading to undesirable outcomes such as a high degree of mechanical complexity and cost. Examples of these parallel interfaces include those using signaling standards such as Gunning Transceiver Logic (“GTL”), Stub-Series Termination Logic (“SSTL”), and High-Speed Transceiver Logic (“HSTL”). Some of these standards require as many as three termination components per signal to implement.
Additional parallel wiring is typically employed when a FPGA array is used to implement multiple card-level interfaces and embedded processor nodes, further increasing circuit complexity. In addition, diverse types of interfaces (VME64x, Race++, and PCI), processors and user hardware modules are often required to communicate with each other on a single card, further complicating inter-card communications issues. For example, current commercial products commonly bridge two standard interfaces together, such as VERSA-Module Europe (“VME”) and Peripheral Component Interconnect (“PCI”) interfaces using parallel bridging chips. Additionally, system-level FPGAs with embedded Power PC (“PPC”) or similar functions require implementation of more processing and interface nodes on a single card. Banking of I/O pins has reduced the need for termination components, but large I/O counts still require many layers to route, driving printed circuit board (“PCB”) layer counts and costs upward.
In addition to parallel wiring configurations, FPGAs on a single card have been interconnected using IEEE 1149 (Joint Test Action Group—“JTAG”) serial interconnections for configuration purposes. However, such JTAG serial interconnections are not suitable for functions such as high-speed data transfer or signal processing. Thus, the use of multiple large FPGAs, embedded processors, and various standard interfaces on a single card present significant problems with card layout/routing and inter-card communication.
In large systems, FPGA and other high-performance computing devices are often buried in many layers of custom I/O connections, making them difficult to access for general use. This characteristic comprises many of the benefits realized from using a reconfigurable circuit.
Medical imaging applications such as Magnetic Resonance Imaging (MRI) and Positron Emission Tomography (PET) are by nature massively parallel calculation-intensive processes. Modern versions of these imaging technologies make extensive use of sophisticated digital signal processing (DSP) algorithms and matrix arithmetic to perform such functions as 3-D reconstruction, color coding, and real-time video display. Seismic oil exploration technology involves not only geology, but also the collection and processing of large amounts of data from geophone and hydrophone arrays. The analysis and multi-dimensional reconstruction of data from such arrays is a parallel problem which involves sophisticated matrix arithmetic as well as DSP.
Pharmaceutical and biotech-related applications such as drug interaction modeling and protein folding simulations are at the same time numerous and by nature extremely calculation-intensive. In one example, a simulation which works out the folding sequence for just 50 amino acid molecules (a very limited set compared to the chains which form real proteins) took 4 to 5 days to run. The computational problems with such calculations are so daunting that some researchers have even turned to volunteer computer networks to get more run-time on these simulations. One such group (the “folding@home” project from Stanford), runs protein folding and aggregation simulations by using the internet to access screen saver programs on volunteer PCs which each run a small piece of the overall parallel calculation.
Special effects in motion pictures and television are also very calculation intensive. Sophisticated effects such as shading, shadowing, texturing, as well as full character animation are becoming increasingly commonplace. One recent movie contained over 6,000 independent artificial intelligence (AI)-driven characters fighting in a lengthy battle sequence. Digital synthesis of a large number of such frames is very costly and time consuming. Because of the long times required to produce the final rendered product, wireframes and other shortcut methods are often used to facilitate the shooting process. As a result, intricate planning and post production is required to make sure that the final effects will fit together with the related live action.